1. Define transistor architecture and design building blocks for new technology nodes;
2. Optimize yield and device performance using analytical skills to enhance SRAM/device outcomes and ensure excellent yield;
3. Design and implement test structures to assess device performance and identify process weaknesses;
4. Communicate effectively and collaborate within cross-functional teams;
5. Integrate devices across various process modules, including creating test keys, executing tape-outs, performing meticulous device analysis, conducting advanced simulations, and ensuring model integrity.

1. Ph.D. in Electronics/Electrical Engineering, Solid State Physics, or a related field from a top-100 QS-ranked university/institution;
2. Strong technical knowledge of device physics, enabling the analysis of parametric data and a firm grasp of integration and yield challenges for key modules and critical device parameters;
3. Proficient in Statistical Process Control (SPC) and/or Design of Experiments (DOE) principles;
4. Experience in integration, SRAM, device measurement (IV/CV), cell design, layout, and simulation (e.g., TCAD/HSPICE) is beneficial but not essential;
5. Excellent communication and teamwork skills, with fluency in English;
6. Skills in AI and programming are preferred (e.g. SQL, python, etc.).